1. Field of the Invention
The present invention relates to a display apparatus and a method of driving a display apparatus.
2. Description of the Related Art
There are a display device including a current-driven light-emitting portion and a display device including the relevant display device. For example, a display apparatus (hereinafter, simply referred to as organic EL display device) including an organic electroluminescence light-emitting portion using electroluminescence (hereinafter, simply referred to as EL) of an organic material is attracting attention as a display device capable of achieving high-luminance light-emission by low-voltage direct-current driving.
Similarly to a liquid crystal display, for example, a display apparatus including an organic EL display device (hereinafter, simply referred to as organic EL display) uses a simple matrix system and an active matrix system as a drive system. The active matrix system has a complex structure but obtains an image with high luminance. An organic EL display device which is driven by the active matrix system includes a light-emitting portion having an organic layer and the like including a light-emitting layer, and a drive circuit for driving the light-emitting portion.
As a circuit for driving an organic electroluminescence light-emitting portion (hereinafter, simply referred to as light-emitting portion), a drive circuit (referred to as 2Tr/1C drive circuit) including two transistors and one capacitor portion is described in JP-A-2007-310311. As shown in FIG. 2, the 2Tr/1C drive circuit includes two transistors of a write transistor TRW and a drive transistor TRD, and one capacitor portion C1. The other area of the source and drain areas of the drive transistor TRD forms a second node ND2, and the gate electrode of the drive transistor TRD forms a first node ND1.
As shown in a timing chart of FIG. 5, during [period-TP(2)1], preprocessing for performing threshold voltage cancel processing is executed. That is, a first node initialization voltage VOfs (for example, 0 V) is applied from a data line DTL to the first node ND1 through the write transistor TRW, which is turned on in response to a scanning signal from a scanning line SCL. Thus, the potential on the first node ND1 becomes VOfs. Further, a second node initialization voltage VCC-L (for example, −10 V) is applied from a power supply portion 100 to the second node ND2 through the drive transistor TRD. Thus, the potential on the second node ND2 becomes VCC-L. The threshold voltage of the drive transistor TRD is represented as a voltage Vth (for example, 3 V). A difference in potential between the gate electrode and the other area of the source and drain areas (hereinafter, referred to as source area for convenience) of the drive transistor TRD becomes equal to or higher than Vth, so the drive transistor TRD is turned on.
Next, during [period-TP(2)2], the threshold voltage cancel processing is performed. That is, in a state where the write transistor TRW is still turned on, the voltage of the power supply portion 100 is changed from the second node initialization voltage VCC-L to a drive voltage VCC-H (for example, 20 V). As a result, the potential on the second node ND2 changes toward a potential obtained by subtracting the threshold voltage Vth of the drive transistor TRD from the potential on the first node ND1. That is, the potential on the second node ND2 in a floating state increases. Then, if the difference in potential between the gate electrode and the source area of the drive transistor TRD reaches Vth, the drive transistor TRD is turned off. In this state, the potential on the second node ND2 is roughly (VOfs−Vth).
Thereafter, during [period-TP(2)3], the write transistor TRW is turned off. Then, the voltage of the data line DTL is set as a voltage corresponding to a video signal [a video signal (drive signal, luminance signal) VSig—m for controlling luminance of the light-emitting portion ELP].
Next, during [period-TP(2)4], write processing is performed. Specifically, the scanning line SCL is at high level, so the write transistor TRW is turned on. As a result, the potential on the first node ND1 increases to the video signal VSig—m.
Let the value of the capacitor portion C1 be c1, and the value of the capacitance CEL of the light-emitting portion ELP be cEL. Let the value of parasitic capacitance between the gate electrode and the other area of the source and drain areas of the drive transistor TRD be cgs. When the potential of the gate electrode of the drive transistor TRD is changed from VOfs to VSig—m (>VOfs), the potential between both ends of the capacitor portion C1 (in other words, the potential between the first node ND1 and the second node ND2) changes in principle. That is, electric charges based on the change amount (VSig—m−VOfs) of the potential on the gate electrode of the drive transistor TRD (=the potential on the first node ND1) are distributed to the capacitor portion C1, the capacitance CEL of the light-emitting portion ELP, and parasitic capacitance between the gate electrode and the other area of the source and drain areas of the drive transistor TRD. If the value cEL is sufficiently larger than the value c1 and the value cgs, there is small change in the potential on the other area of the source and drain areas of the drive transistor TRD (second node ND2) based on the change amount (VSig—m−VOfs) of the potential on the gate electrode of the drive transistor TRD is small. In general, the value cEL of the capacitance CEL of the light-emitting portion ELP is larger than the value c1 of the capacitor portion C1 and the value cgs of parasitic capacitance of the drive transistor TRD. Therefore, for convenience of description, description will be provided without taking into consideration the change in the potential on the second bode ND2 due to the change in the potential on the first node ND1. The drive timing chart shown in FIG. 5 is provided without taking into consideration the change in the potential on the second node ND2 due to the change in the potential on the first node ND1.
In the above-described operation, in a state where a voltage VCC-H is applied from the power supply portion 100 to one area of the source and drain areas of the drive transistor TRD, the video signal VSig—m is applied to the gate electrode of the drive transistor TRD. For this reason, as shown in FIG. 5, during [period-TP(2)4], the potential on the second node ND2 increases. The increased amount ΔV of the potential (potential correction value) will be described below. When the potential of the gate electrode of the drive transistor TRD (first node ND1) is Vg, and the potential of the other area of the source and drain areas (second node ND2) is Vs, if the increased amount ΔV of the potential on the second node ND2 is taken into consideration, the value Vg and the value Vs are as follows. The difference in potential between the first node ND1 and the second node ND2, that is, the potential difference Vgs between the gate electrode and the other area of the source and drain areas serving as a source area of the drive transistor TRD can be expressed by Equation (A).Vg=VSig—m Vs≅VOfs−Vth Vgs≅VSig—m−(VOfs−Vth)  (A)
That is, Vgs obtained during the write processing to the drive transistor TRD depends only on video signal VSig—m for controlling luminance in the light-emitting portion ELP, the threshold voltage Vth of the drive transistor TRD, and the voltage VOfs for initializing the potential of the gate electrode of the drive transistor TRD. There is no relation between Vgs and the threshold voltage Vth-EL of the light-emitting portion ELP.
Next, mobility correction processing will be described in brief. In the above-described operation, during the write processing, the mobility correction processing is also performed for changing the potential of the other area of the source and drain areas of the drive transistor TRD (that is, the potential on the second node ND2) in accordance with the characteristics of the drive transistor TRD (for example, the magnitude of mobility μ and the like).
As described above, in a state where the voltage VCC-H is applied from the power supply portion 100 to one area of the source and drain areas of the drive transistor TRD, the video signal VSig—m is applied to the gate electrode of the drive transistor TRD. As shown in FIG. 5, during [period-TP(2)4], the potential on the second node ND2 increases. As a result, when the value of the mobility μ of the drive transistor TRD is large, the increased amount ΔV (potential correction value) of the potential in the source area of the drive transistor TRD increases. When the value of the mobility μ of the drive transistor TRD is small, the increased amount ΔV (potential correction value) of the potential in the source area of the drive transistor TRD decreases. The potential difference Vgs between the gate electrode and the source area of the drive transistor TRD is transformed from Equation (A) into Equation (B).Vgs≅VSig—m−(VOfs−Vth)−ΔV  (B)
As described below, qualitatively, control is preferably performed such that, as the value VSig—m decreases, [period-TP(2)4] is extended. JP-A-2008-9198 discloses a configuration in which the falling edge of the scanning signal is inclined so as to control the length of the period in accordance with the value of the video signal.
Through the above-described operations, the threshold voltage cancel processing, the write processing, and the mobility correction processing are completed. In the commencement of subsequent [period-TP(2)5], the write transistor TRW is turned off by the scanning signal from the scanning line SCL, so the first node ND1 is in a floating state. The voltage VCC-H is applied from the power supply portion 100 to one area of the source and drain areas (hereinafter, also referred to as drain area for convenience) of the drive transistor TRD. As a result, the potential on the second node ND2 increases, the same phenomenon as in a so-called bootstrap circuit occurs in the gate electrode of the drive transistor TRD, and the potential on the first node ND1 also increases. The potential difference Vgs between the gate electrode and the source area of the drive transistor TRD is maintained at the value of Equation (B). A current flowing in the light-emitting portion ELP is a drain current Ids flowing from the drain area of the drive transistor TRD to the source area. If the drive transistor TRD ideally operates in a saturation area, the drain current Ids can be expressed by Equation (C). The light-emitting portion ELP emits light with luminance according to the value of the drain current Ids. A coefficient k will be described below.Ids=k·μ·(Vgs−Vth)2=k·μ·(VSig—m−VOfs−ΔV)2  (C)
From Equation (C), the drain current Ids is proportional to the mobility μ. Meanwhile, as the drive transistor TRD has a larger mobility μ, the more the potential correction value ΔV increases, and the value (VSig—m−VOfs−ΔV)2 in Equation (C) decreases. Thus, variation in the drain current Ids due to variation in the mobility μ of the drive transistor can be corrected.
The operation of the 2Tr/1C drive circuit described above in brief will be described below in detail.